Multistable circuit including elements preset for conduction

ABSTRACT

A multistable circuit includes a plurality of latching pairs, each preferably comprising transistors connected in a feedback circuit. Each latching pair is coupled to a transistor of the next latching pair. for presetting such transistor for conduction. The latching pairs alternately receive current from a current switching means, and when the current is switched, the latching pair having the preset transistor immediately conducts.

United States Patent 8 Moriyasu [54] MULTISTABLE CIRCUIT INCLUDINGELEMENTS PRESET FOR CONDUCTION [72] lnventor: Hiro Morlyasu, Portland,Oreg. [73] Assignee: Tektronix,1nc., Beaverton, Oreg. 22 Filed: Jan. 21,1969 [21] Appl. No.: 792,501

[52] US. Cl; ..307/225, 307/223, 307/279, 307/289, 307/313 [51] Int. Cl..H03lt 23/08, H031: 23/22, H03k 3/26 [58] Field of Search..307/220-226, 255, 307/288, 279, 289, 291, 304, 313

[5 6] References Cited UNITED STATES PATENTS Pecar 4....307/223 R Brown..307/288 X Ross .307/223 Harrick .307/223 Shockley ..307/221 3,081,4083/1963 3,381,137 4/1968 2,856,544 10/1958 3,033,993 5/1962 2,967,952l/l96l 8 1451 Aug..1, 1972 4/1965 3,319,086 5/ 1967 Yee ..307/2883,329,834 7/1967 Klinikowski ..307/223 3,469,110 9/1969 Sherman..307/223 OTHER PUBLICATIONS Pub 1. Helpful Transistor Analog:4-layerpnpn 2 Transistors by Stasior in Electronics dated August 10,1964, pages 66 to 73.

Primary Examiner-Stanley D. Miller, Jr. Attorney-Buckhorn, Blore,Klarquist and Sparkman [57] ABSTRACT A multistable circuit includes aplurality of latching pairs, each preferably comprising transistorsconnected in a feedback circuit. Each latching pair is cou-.

pled to a transistor of the next latching pair. for

- presetting such transistor for conduction. The latching pairsalternately receive current from a current switching means, and when thecurrent is switched, the latching pair having the preset transistorimmediately conducts.

17 Claims, 5 Drawing Figures Durio, Jr .Q ..307/223 PATENTEDAuc H9723.681.617

sum 1 OF 3 FIG. I

m HIRO MORIYASU wvnvroes.

l Q5 BY BUG/(HORN, BLORE, KLAROU/ST 8 SPAR/(MAN ATTOR/VfYS PATENTEDMII;1 m2 SHEET 3 OF 3 HI RO MORIYASU lNVE/VTOR B) Buck/10m BLORE, KLAROU/Sfa SPAR/(MN ATTORNEYS MULTISTABLE CIRCUIT INCLUDING ELEMENTS PRESET FORCONDUCTION BACKGROUND OF THE INVENTION A binary divider or flip-flop isone of the basic circuits in computers, frequency counters, and otherdigital equipment. The conventional binary flip-flop uses chargecommutative devices such as capacitors or.

is also critical as to stray capacitance and transistor high frequencyparameters. Moreover, the conventional circuit is usually sensitive tothe input drive rise time.

SUMMARY OF THE INVENTION According to the present invention, amultistable circuit includes a plurality of latching pairs or circuitswherein the latching pairs or circuits are adapted to operateconsecutively so that only one from a number thereof is on at one time.Coupling means extend from each latching circuit to an active element ofthe next latching circuit for presetting the same for conduction.Current switching means transfer current between alternate latchingcircuits, and when switching takes place, the latching circuit includingthe preset element will immediately conduct. The circuit is operative atfrequencies from substantially zero to 600 megahertz.

It is an object of the present invention to provide an improvedmultistable circuit operative over a wide frequency range.

It is another object of the present invention to provide an improvedmultistable or divider circuit which is substantially insensitive toinput drive rise time. 7

It is another object of the present invention to provide an improvedmultistable circuit which does not employ commutative time constantmeans.

It is another object of the present invention to provide an improvedmultistable circuit which is relatively simple, and which is easilyadapted to integrated circuit techniques. I

The subject matter which I regard as my invention is particularlypointed out and distinctly claimed in the concluding portion of thisspecification. The invention, however, both as to organization andmethod of opera- DETAILED DESCRIPTION Referring to FIG. 1, a multistablecircuit according to the present invention comprises a plurality oflatching circuits preferably comprising pairs of transistors. A firstsuch pair comprises a first transistor 0, and a second transistor Q. Asecond pair comprises transistors Q and 06, a third 0 and Q1, and afourth Q and Q The transistors of each pair are intercoupled in feedbackfashion so that if one transistor conducts, both will tend to conductheavily. Thus, the collector of Q, is coupled to the base of 0 by meansof resistor 10, while the collector of O is similarly connected to' thebase of Q, employing resistor 12. Resistor 14 returns the base of Q, toa positive voltage, while resistor 16 returns the base of Q, to anegative voltage. Coupling means, comprising resistor 18, couples thecollector of Q to the base of Q A current source, i provides current atthe emitters of Q 5 and Q while a current source i provides current atthe emitters of Q and Q. In the embodiment of FIG. 1, the firsttransistors of each pair,

i.e., transistors, Q Q Q and Q, are suitably NPN type, while the secondtransistor of each pair, i.e., transistors Q5, Q6, Q and Q are ofcomplementary or PNP type.

A current switching circuit comprising transistors Q and Q is employedfor providing current alternatively at theemitters of Q and Q, or at theemitters of Q and Q The emitters of Q and Q10 are connected to a cur- Irent source i while the collectors of Q and Q10 are connected to theemitters of Q and Q and the emitters of Q and 0,, respectively. The baseof Q1 is returned to a negative voltage through resistor 20, and toground via Zener diode 22. The base of O is also returned to a negativevoltage employing resistor 24, while a Zener diode 26 couples the baseof O to an input terminal 28.

Successive latching circuits are intercoupled in the same way asdescribed above in connection with I latching circuits Q Q and Q Q andare arranged in tion, together with further advantages and objectsthereof, may best be understood by reference to the followingdescription taken in connection with the accompanying drawings whereinlike reference characters refer to like elements.

DRAWINGS circuit acconsecutive manner, with alternate transistor pairsreceiving current via 0,, or via Q10. Pairs receiving current from Oalso receive current from source i while pairs receiving current from Qalso receive current from source i Resistor 30 from the collector of Q,is connected at point Y to the base of O to provide a continuous circuitconnection.

In considering operation of the circuit, let us assume that transistorsQ and Q are conducting. Since the collector of each is connected to thebase of the other, a feedback circuit is established, each holding theother in conduction. At this time, Q is on, providing current throughtransistor 0, and resistors 32 and 34 to a positive voltage source. Thedrop in resistor 34 insures the conduction of 0,, whereby current i;,flows through transistor Q and resistors 36 and 38. Since the base of Q,is connected to the junction between resistors 36 and 38, continuedconduction of Q, is assured.

At the same time, 0,, being coupled to the base of 0,,

via resistor 30, provides a part of the current i 1 from Q10 throughresistor 14 providing a drop in resistor 14 effective for turning Q on.At this time, Q will not be on inasmuch as no current is providedtherefor. However, since 0,, conducts, the latching circuit comprising Qand Q, is preset so that when the current i, is switched, the pair 0,, Qwill immediately go into feedback conduction. 0;, draws current throughresistors 12 and 16 providing a voltage at the base of Q1 presetting Q,for

conduction. Thus, when a positive pulse is applied at.

terminal 28, the base of Q9 Previously in effect tied to a negativevoltage, will be raised via Zener diode 26, causing Q, to conduct. Sincethe transistors Q, and Q are connected differentially, Q, will draw thecurrent previously coupled through Q10, and Q10 will cease conduction.Q, will now deliver current i, to the emitter of Q and transistor Q willconduct immediately since it was preset for conduction. Q now presets Qvia resistor l8. I

.Thus, when pair Q Q conducts, transistor Q of the next pair conductsand transistor Q, is preset for conduction. Q, conducts whenever andjust as soon as current is provided via transistor'Q Then when thesignal input again goes negative, transistor Q, will be shut off, sincethe negative-going signal will drive the base thereof'below cutoff, andQ will conduct. Since transistor Q, is conducting, transistor Q, will beturned on at its base, and current i, will immediately flow throughtransistor 0,. As a result, feedback conduction I between transistors Q,and Q. is established. In this cir- Q, and Q alternately conduct. Thesignal at the collectors of Q, and Q is substantially a square wave withpositive altemations being designated T and T while negativealternations are designated T, and T At the time T or when Qg'firstconducts, transistor Q, will conduct and provide a negative-output, asillustrated. At time T,, transistor Q, conducts providing anegativegoing output designated Q, in FIG. 2, etc. As hereinbeforementioned,Q,"is on at the same time Q is on, but so is 0,. Q, continuesto conduct at the time T, when Q, is on. Transistors Q Q Q and Q,conduct in that order and then, since Q, is connected to Q, the cyclerepeats. Transistors- Q; through Q turn on and off at every othertransition of the input waveform thus,

representing a binary countdown by a factorof two in terms of the inputfrequency. The circuit is useful for any dividing function, ring counterfunction, or the like. Outputs are suitably derived from the collectorsof transistors Q, through Q, by means of isolating transistors (notshown in this embodiment) or alternatively from the collectors of Q,through 0,, by means of isolating transistors.

Inthe circuit of FIG. 1, only the latching circuit in- "cluding a presettransistor will come on next when the current is switched betweentransistors Q, and Q10- The "non-preset transistor connected tothecollector of Q or Q is biased off. As a latching circuit goes intofeedback conduction, atr'ansistor of the next following pair 1 is presetfor maintaining the proper sequence in each case.

The circuit is not sensitive to the frequency of input presentedatterminal 28. Thewaveform may be very slowly changing and the circuitwill operate as described. However, the circuit will continue toopera'teat high frequencies. For example in integrated circuitoperation, the circuit has operated up to a frequency of 600 megahertz.

In FIG. 3, another embodiment of the present invention is illustrated,wherein the latching circuits are formed slightly differently. Thistime, thefirst latching circuit comprises a first transistor Q, and asecond transistor 0,. The remaining latching circuits comprisetransistors Q, and Q Q and Q and Q and Q5, respectively. Thus, when thetransistor 0 conducts, current is drawn through resistors 42 and Minseries from a positive source, wherein 'thevoltage at the junctionbetween the resistors causes transistorQ, to conduct. Similarly,transistor 0,, draws current from a positive source through resistors 46and 48, raising the voltage at the base of Q and holding the lattertransistor in a conducting state. At this time, 'it is assumed a currenti, is provided through transistor 0, to transistor 04 in the same manneras hereinbefore described in connection with the embodiment of FIG. 1.

The collector of Q, is coupled to the base of Q with resistor 50 atpoint Z, so also at this time current is coupled from the collector ofQ; through resistor 50 and resistor 52 to ground. The voltage dropacross resistor 52 raises the base voltage of transistor Q, presettingtransistor Q for conduction. As soon as a positivegoing signal isreceived at terminal 28, current is delivered through transistor Q, tothe emitter of Q, and the latter immediately conducts inasmuch as it ispreset for conduction. As ,0, conducts, current is drawn throughresistors 54 and 56 thereby lowering-the voltage at the base of Q6,whereby Q, conducts. As'Q, conducts, current flows through resistors 58and 52 for maintaining the voltage across resistor52 at a value forretaining Q, in a conducting state. As the current i,- transfers from Qto Q9. the source'of current for resistor 52 shifts from Q to 0,, but issufficient for maintaining Q, in conduction. e

A further modification of theinvention is illustrated in FIG. 4. Thiscircuit is similar to the FIG. 3 circuit, and like elements aredesignated similarly. The resistor between the collector of 'a firsttransistor of a given latching circuit and the base of a secondtransistor of the same latching circuit has been eliminated. Forexample, the collector of first transistor Q, is directly connected tothe base-of second transistor Q, without an intervening resistor, sincesuch resistor is not necessary to circuit operation, and the schematicdiagram is thereby simplified. With switch 60 in-the position shown,circuit operation will be identical to thatof the circuit of FIG. 3.That is, the feedback conduction in each latching pair presets atransistor of the next pair such that when the current shifts inresponse to an input signal, the next latching pair will conduct. Thus,as current shifts from Q to Q, transistors Q and Q, cease conductionwhile transistors Q, and Q, start conduction. However, the FIG. 4circuit is provided with additional transistors Q Q Q and 0,. Each ofthe last mentioned transistors comprises an additional second transistorfor each latching pair. When switch 60 is in the position shown, theseadditional transistors are not energized. However, when the switch isthrown from position F to position B, transistors Q Q.', Q,', and Q, areenergized in place of the non-primed second transistors. In the latterevent, the latching pairs comprise transistors Q and Q transistors Q,and Q transistors Q and Q and transistors Q and Q e t Let us assume thattransistors Q, and Q, are conducting with switch 60 thrown into position8. Current from the collector of Q flows through resistor 62 maintainingthe conduction of transistor Q while the collector current fromtransistor 0,, flows through resistors 64 and 66 for maintainingtransistor Q in a conducting state. The collector of transistor Q isalso coupled to the base of transistor via resistor 68 and a currentflows through resistor 68 and resistor 70 7 located between the base oftransistor 0;, and ground. Transistor 0;, is thus preset for conduction.Now, when a positive-going signal is received at terminal 28, andcurrent i switches from transistor 0, to transistor Q transistor 0;,will conduct instead of transistor 0, inasmuch as transistor Q waspreset through resistor 68. With succeeding transitions at inputterminal 28, the multistable circuit will operate in a reverse directionsuch that each latching pair in succession from right to left becomesconductive and presets the next. Switch 60 is thrown to R for reverseoperation, and to F for forward operation.

A further embodiment of the present invention is illustrated in FIG. andemploys entirely NPN transistors. The circuit is therefore easilyimplemented in an integrated circuit construction. It will beappreciated by those skilled in the art that the various diodesillustrated in the circuit are easily fabricated in the same integratedcircuit construction with the NPN transistors. The transistor pairscomprising latching circuits respectively comprise transistors Q and Qtransistors Q and Q transistors Q and Q and transistors Q and Q In theFIG. 5 circuit, the emitters of transistors Q and Q receive current fromthe collector of Q while the emitters of transistors Q and Q aresimilarly connected to receive current from the collector of Q Thecollector of Q is directlyconnected to the base of Q while the emitterof 0., is returned to ground through a resistor 72. Transistor Q; is oneof the differential pair of transistors and the emitter of transistor Q,is connected to the emitter of transistor On, the latter having its baseconnected to a source of reference voltage, R. The collector oftransistor Q is returned to a positive voltage, and the collector oftransistor O is coupled to the same positive voltage through resistor74. Transistors Q and Q comprise a current switching pair ordifferential amplifier circuit for switching the current passing throughresistor 72 so that it flows either to 0 or Q The collector oftransistor O is also connected to the cathode of a Zener diode 76, theanode of which is connected to the base of transistor 0,. The anode ofdiode 76 is returned to ground via resistor 78. Also, the collector oftransistor O is coupled to the base of transistor Q of the next latchingcircuit by way of Zener diode 80 having its anode connected to the baseof Q as well as through resistor 82 to ground.

The collector of transistor O is coupled through resistor 84 to theemitter of an isolation transistor 86 having its base connected to thejunction between a diode 88 and a resistor 90 interposed in that orderbetween a positive voltage and ground. A resistor 92 connects thecollector of transistor 86 to a positive voltage, and an output terminal94 is also connected to the collector of transistor 86. Transistor 86operates as a common base transistor amplifier for isolating the 0,, Qlatching pair from an output load which may be connected at terminal 94.

Each of the stages is substantially identical, and the last latchingpair, Q.,, Q is connected to the first latching pair at point X. Thecollector of transistor 0,, is connected to a positive voltage throughresistor 96 and the emitter of transistor 0, is returned to ground viaresistor 98. The emitter of transistor Q14 is also connected to theemitter of transistor Q while the collector of Q is connected to apositive voltage. A resistor 100 is located between the collector oftransistor Q, and the emitter of an isolating transistor 102. Zenerdiode 104 is disposed between the collector of transistor Q and the baseof transistor 0,. Also a Zener diode 106 is connected between point Xand the base of 0,, the anode of the Zener diode being connected to thebase of 0,.

Let us assume transistor 10 is on and that the feedback pair comprisingtransistors Q and Q; is operated. Transistor Q, is conducting andtransistor 0,, is nonconducting. The current from the collector of Qpasses through 0, and resistor 100 dropping the voltage at the base oftransistor Q Transistor Q1 conducts instead of Q and voltage at thecollector of O is high. The voltage level at the collector of transistor0,, is reduced by Zener diode 104 so that it is appropriate forapplication at the base of transistor 0., for maintaining the conductionof Q Transistors Q4 and 0 are thus connected in a feedback arrangement.Also, the voltage at the collector of transistor O is applied at point Xto Zener diode 106, located between the collector of Q and the base of QTherefore, the voltage at the base of Q presets Q for conduction. Now,when a positive-going voltage is received at terminal 28 and current ishifts, transistor Q will conduct inasmuch as the latter is the onlytransistor among transistors Q Q Q and Q which has been preset forconduction. The change in the condition of Q1, of course, is coupled toterminal 94 via transistor 86.

The circuits according to thepresent invention are not encumbered byrate or rise time determining commutation components, but rather thenext stage to be on is preset at the same time the previous stage goesinto conduction, and therefore commutation problems are substantiallynonexistent. As hereinbefore mentioned, the circuit will operate andkeep step with an input changing at an exceedingly low or substantiallyd.c. switching rate, up to a signal of several hundred megahertz. Thevarious multistable circuit stages themselves provide suitably dividedoutputs, or may be combined in various manners to produce a desiredoutput pulse configuration. Although each of the circuits illustratedincludes four 4 latching stages, it will be appreciated that stages maybe added as desired. E.G., two of the-circuits of the present inventionmay be employed together, with the output of each circuit operating asthe input of the other circuit.

While I have shown and described several embodiments of my invention, itwill be apparent to those skilled in the art that many changes andmodifications may be made without departing from my invention in itsbroader aspects.

I claim:

1. A multistable circuit comprising: a plurality of latching circuitseach comprising a pair of transistors interconnected in a feedbackarrangement,

and means for directly and continuously coupling a first feedback pairto a control electrode of a transistor of a second feedback pair so thatthe transistor of the second feedback pair is preset for conduction atthe time that feedback conduction takes place in the first pair.

2. The circuit according to claim 1 wherein saidtransistor of saidsecond pair is provided current so that it conducts substantialoperating current at the same time the first pair conducts.

3. The circuit according to claim 1 further including 4 conduction inone. transistor tends to predetermine the state of the other transistor,

means for coupling a collector of one transistor 0 each priorpair to thebase of a transistor of a next pair in sequence for presetting thattransistor of the next pair for conduction, at the time that feedbackconduction takes place in the prior pair, and current switching means.for switching a predetermined supply current between alternate feedbackpairs respectively coupled by said 7 coupling means so'that when currentis switched, the transistor pair including the preset transistor goesinto feedback conduction. 5. The circuit according .to claim 4. whereina first transistor of each pair is connected to said current switchingmeans and wherein said coupling means couples the collectorv of a secondtransistor of each pair to the base of the firsttransistor'of the nextpair for resetting the same. v

6. The circuit according to claim 4 wherein the first transistor of eachpair is connected to saidcurrent switching means and wherein thecollector' of the first transistor of each pair is coupled by saidcoupling means to the second transistor in the next pair for tuming onsuch second transistor of the next pair and presetting the firsttransistor of thenext pair.

. 7. The circuit according to claim 4 further including additionalsecond transistors wherein each-additional second transistor is alsocoupled with one of said first transistors to form. a. feedback pair andadditional coupling means for coupling each additional second transistorto a first transistor of a prior pair,

and means for selectively providing current to said second transistorsor to said additional second transistors for securing reversiblepresetting in said multistable circuit.

8. The circuit according to claim 4 wherein said first and secondtransistors are of opposite conductivity types, and wherein bothtransistors of a given pair are adapted to conduct at the same timeduring feedback operation.

9. The circuit according to claim 4 wherein the coupling means from alast transistor pair in sequence is coupled for presetting atransistorof a first transistor pair in the same sequence.

, 10. The circuit according to claim 4 wherein said first and secondtransistors are of complementary conductivity types, and furtherincluding a second source of current for said second transistors. I

ll.-The circuit according to claim 41 wherein said firstandsec ndtr 'trs eof sam d "t type and furthe f l c udir ig Z ier dropping means forcoupling the output of each second transistor to the input of the firsttransistor of the same pair. i a

l2..The circuit according to claim 11 wherein said coupling meansbetween a feedback pair and a transistor of the next pair for presettingthe same comprises a Zener diode.

13. The circuit according'to claim 4 wherein said first and secondtransistors are of the same conductivity type and further including anadditional transistor as-' sociated with each pair connected in adifferential amplifier circuit with the second transistor of each pair.

14. A multistable circuitcomprising:

a plurality of latching circuits each including a feedback pair ofactive elements, wherein said first ones of said latching circuits areadapted to al-- temate in operating sequence of feedback conduction withsecond ones of said latching circuits, means for applying a voltage froma given latching circuit to one of the active elements of the nextlatching circuit for presetting such element atthe time when feedbackconduction takes place in the given latching" circuit, 1 and meansforproviding a current to the said one element of the next latching circuitso that substantial current conduction takes place therein as the sameis preset at the same time that feedback conduction takes place in thegiven latching circuit,

therebyenabling subsequent feedback conduction inthe next latchingcircuit. 15. A multistable circuit comprising:

a plurality of latching circuits, each including afeed- I means forapplying a voltage from the said given feedback circuit to an activeelement of a=prior latching circuit in sequence,

and means for selecting between forward and reverse operation of suchmultistable circuit.

16. A multistable circuit comprising: I

a plurality of latching circuits each comprising a pair of transistorsinterconnected in a feedback arrangement, said transistors havingcollector electrodes and control electrodes,

and means for directly andcontinuously coupling a collector electrode ofa transistor of a first feedback pair to a control electrode of atransistor of a second feedback pair so that the transistor of thesecond feedback pair is preset for conduction at the time that feedbackconduction takes place in the first feedback pair.

17. The circuit according to claim 16 wherein said direct coupling meanscomprises a resistor.

l III UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,681,617 Dated Au gust 1, 1972 Inventor(s) HIRO MORIYASU' It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

C01. 3, line 35, "negative-output" should be -negative-going output--Signed and sealed this 9th day of January 1973 (SEAL) Attest:

EDWARD M.FLETCHER,JR. I ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents FORM PO-1050 (10-69) USCOMNPDC 5O37 p6 u.s. covnnmzm'PRINTING omc: I!" o-au-J:

1. A multistable circuit comprising: a plurality of latching circuitseach comprising a pair of transistors interconnected in a feedbackarrangement, and means for directly and continuously coupling a firstfeedback pair to a control electrode of a transistor of a secondfeedback pair so that the transistor of the second feedback pair ispreset for conduction at the time that feedback conduction takes placein the first pair.
 2. The circuit according to claim 1 wherein saidtransistor of said second pair is provided current so that it conductssubstantial operating current at the same time the first pair conducts.3. The circuit according to claim 1 further including current switchingmeans for switching supply current between transistors of said first andsecond pairs.
 4. A multistable circuit comprising: a plurality offeedback circuits each comprising a first transistor and a secondtransistor and coupling means between said transistors so thatconduction in one transistor tends to predetermine the state of theother transistor, means for coupling a collector of one transistor ofeach prior pair to the base of a transistor of a next pair in sequencefor presetting that transistor of the next pair for conduction, at thetime that feedback conduction takes place in the prior pair, and currentswitching means for switching a predetermined supply current betweenalternate feedback pairs respectively coupled by said coupling means sothat when current is switched, the transistor pair including the presettransistor goes into feedback conduction.
 5. The circuit according toclaim 4 wherein a first transistor of each pair is connected to saidcurrent switching means and wherein said coupling means couples thecollector of a second transistor of each pair to the base of the firsttransistor of the next pair for resetting the same.
 6. The circuitaccording to claim 4 wherein the first transistor of each pair isconnected to said current switching means and wherein the collector ofthe first transistor of each pair is coupled by said coupling means tothe second transistor in the next pair for turning on such secondtransistor of the next pair and presetting the first transistor of thenext pair.
 7. The circuit according to claim 4 further includingadditional second transistors wherein each additional second transistoris also coupled with one of said first transistors to form a feedbackpair and additional coupling means for coupling each additional secondtransistor to a first transistor of a prior pair, and means forselectively providing current to said second transistors or to saidadditional second transistors for securing reversible presetting in saidmultistable circuit.
 8. The circuit according to claim 4 wherein saidfirst and second transistors are of opposite conductivity types, andwherein both transistors of a given pair are adapted to conduct at thesame time during feedback operation.
 9. The circuit according to claim 4wherein the coupling means from a last transistor pair in sequence iscoupled for presetting a transistor of a first transistor pair in thesame sequence.
 10. The circuit according to claim 4 wherein said firstand second transistors are of complementary conductivity types, andfurther including a second source of current for said secondtransistors.
 11. The circuit according to claim 4 wherein said first andsecond transistors are of the same conductivity type and furtherincluding Zener diode voltage dropping means for coupling the output ofeach second transistor to the input of the first transistor of the samepair.
 12. The circuit according to claim 11 wherein said coupling meansbetween a feedback pair and a tRansistor of the next pair for presettingthe same comprises a Zener diode.
 13. The circuit according to claim 4wherein said first and second transistors are of the same conductivitytype and further including an additional transistor associated with eachpair connected in a differential amplifier circuit with the secondtransistor of each pair.
 14. A multistable circuit comprising: aplurality of latching circuits each including a feedback pair of activeelements, wherein said first ones of said latching circuits are adaptedto alternate in operating sequence of feedback conduction with secondones of said latching circuits, means for applying a voltage from agiven latching circuit to one of the active elements of the nextlatching circuit for presetting such element at the time when feedbackconduction takes place in the given latching circuit, and means forproviding a current to the said one element of the next latching circuitso that substantial current conduction takes place therein as the sameis preset at the same time that feedback conduction takes place in thegiven latching circuit, thereby enabling subsequent feedback conductionin the next latching circuit.
 15. A multistable circuit comprising: aplurality of latching circuits, each including a feedback pair of activeelements, wherein first ones of said latching circuits are adapted toalternate in operating sequence of feedback conduction with second onesof said latching circuits, means for applying voltage from a givenlatching circuit to one of the active elements of the next latchingcircuit causing such element to be preset for conduction at the timewhen feedback conduction takes place in the given latching circuit,means for applying a voltage from the said given feedback circuit to anactive element of a prior latching circuit in sequence, and means forselecting between forward and reverse operation of such multistablecircuit.
 16. A multistable circuit comprising: a plurality of latchingcircuits each comprising a pair of transistors interconnected in afeedback arrangement, said transistors having collector electrodes andcontrol electrodes, and means for directly and continuously coupling acollector electrode of a transistor of a first feedback pair to acontrol electrode of a transistor of a second feedback pair so that thetransistor of the second feedback pair is preset for conduction at thetime that feedback conduction takes place in the first feedback pair.17. The circuit according to claim 16 wherein said direct coupling meanscomprises a resistor.